1. Field of the Invention
The present invention relates to a driver for liquid crystal display and particularly to a driver for driving a liquid crystal panel used as a display of portable computers, PDA (Personal Digital Assistants), or portable electronic equipment such as mobile phones and PHS (Personal Handy-phone System).
2. Description of Related Art
As a driver for liquid crystal display used in portable electronic equipment, a liquid crystal display driver which outputs gray scale voltages in time-sharing manner from a unit amplifier for at least each unit pixel of a liquid crystal panel is used. FIG. 7 is a block diagram showing an exemplary configuration of drivers of such a liquid crystal panel 100. In this example, the resolution of the liquid crystal panel 100 is 176×220 pixels. One pixel is composed of three sub-pixels of Red (R), Green (G) and Blue (B), and accordingly there total 528×220 sub-pixels. The time-sharing output of this example divides outputs into three (R, G, and B) portions. The liquid crystal panel 100 includes a total 176 sets of R data lines 101a, G data lines 101b and B data lines 101c which are arranged crosswise and each extends lengthwise on FIG. 7, and 220 lines of scan lines 102 which are arranged lengthwise and each extends crosswise on FIG. 7, though only one of them is illustrated in FIG. 7. Each sub-pixel is composed of a TFT 103, a pixel capacitor 104, and a liquid crystal element 105. The gate terminal of the TFT 103 is connected to the scan line 102, and the source (drain) terminal of the TFT 103 is connected to data lines 101a, 101b or 101c. The drain (source) terminal of the TFT 103 is connected to the pixel capacitor 104 and the liquid crystal element 105. The terminals 106 of the pixel capacitor 104 and the liquid crystal element 105 which are not connected to the TFT 103 may be connected to a common electrode, though not shown. The input terminals of the 176 sets of data lines 101a, 101b and 101c are respectively connected to the output terminals a, b and c of change-over switches 1071 to 107176 with 1 input and 3 outputs.
A driving circuit of the liquid crystal panel 100 is composed, schematically, of a controller 200, a data driver 300, and a scan driver 400. The driving circuit is normally in the form of an integrated circuit (IC). In portable electronic equipment, the controller 200 and the data driver 300, or the controller 200, the data driver 300, and the scan driver 400, for example, may be integrated into one IC chip.
The controller 200 converts digital image data which is supplied from outside to digital gray scale data which can be processable by the data driver 300 and also controls the timings of the data driver 300, the scan driver 400, and the change-over switches 1071 to 107176 of the liquid crystal panel 100.
The data driver 300 converts the gray scale data of one scan line 102 which is supplied from the controller 200 into an analog gray scale voltage for each of the scan lines 102 (i.e. in each horizontal period) and applies the analog gray scale voltage to the data lines 101a, 101b and 101c in time-sharing manner.
The scan driver 400 sequentially drives the scan lines 102 in each horizontal period to turn ON the TFTs which are connected to each scan line 102, thereby supplying the gray scale voltage which is applied to the data lines 101a, 101b and 101c to the liquid crystal elements 105.
The controller 200 includes a data processor 210 and a control signal generator 220 as shown in FIG. 8.
The data processor 210 retrieves image data supplied from outside, e.g. Red data (Rdata), Green data (Gdata) and Blue data (Bdata) of 6 bit each, at the timing of a dot clock Dclk also supplied from outside. Then, it converts the Rdata, Gdata and Bdata into Red data (RD), Green data (GD) and Blue data (BD) of 6 bit each, which are gray scale data that can be driven by the data driver 300.
The control signal generator 220 generates a signal for controlling the timings of the data driver 300, the scan driver 400, and the change-over switches 1071 to 107176 of the liquid crystal panel 100 based on a dot clock Dclk, a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync which are supplied from outside. The control signal generator 220 also generates a strobe signal STB, a clock HCK, a horizontal start pulse HST, switch control signals RS1, GS1 and BS1, and an output control signal AS for the data driver 300. The control signal generator 220 further generates a clock VCK and a vertical start pulse VST for the scan driver 400. The control signal generator 220 generates switch control signals RS2, GS2 and BS2 for the change-over switches 1071 to 107176 of the liquid crystal panel 100.
The data driver 300 is described hereinafter. As shown in FIG. 9, the data driver 300 includes a shift register 310, a data register 320, a data latch circuit 330, a switching circuit 340, a D/A converter 350, and an output circuit 360.
The shift register 310 performs shift operation for shifting the horizontal start pulse HST supplied from the controller 200 and outputs total 176 bits of parallel sampling pulses SP1 to SP176 in synchronization with the clock HCK also supplied from the controller 200.
The data register 320 retrieves the each 6-bit gray scale data RD, GD and BD supplied from the controller 200 as gray scale data RD1, GD1 and BD1 to RD176, GD176 and BD176 in synchronization with the sampling pulses SP1 to SP176 supplied from the shift register 310, and supplies them to the data latch circuit 330.
The data latch circuit 330 latches the gray scale data RD1, GD1 and BD1 to RD176, GD176 and BD176 supplied from the data register 320 in synchronization with the rising edge of the strove signal STB supplied from the controller 200. The data latch circuit 330 then retains the latched gray scale data RD1, GD1 and BD1 to RD176, GD176 and BD176 until the strobe signal STB is supplied next, which is, for one horizontal period.
The switching circuit 340 includes 176 sets of change-over switches 3411 to 341176 with 3 inputs and 1 output. In synchronization with the switch control signals RS1, GS1 and BS1 supplied from the controller 200, the switching circuit 340 supplies the gray scale data RD1, GD1 and BD1 to RD176, GD176 and BD176 supplied from the data latch circuit 330 in time-sharing manner in the order of (RD1 to RD176)→(GD1 to GD176)→(BD1 to BD176) to the D/A converter 350.
Based on the values of the 6-bit gray scale data RD1, GD1 and BD1 to RD176, GD176 and BD176 which are time-sharingly supplied from the switching circuit 340, the D/A converter 350 time-sharingly selects one gray scale voltage from 64 analog gray scale voltages V1 to V64, and supplies gray scale voltages RV1, GV1 and BV1 to RV176, GV176 and BV176 in time-sharing manner in the order of (RV1 to RV176)→(GV1 to GV176)→(BV1 to BV176) to the output circuit 360.
The output circuit 360 includes amplifiers 3611 to 361176, switches 3621 to 362176 which are respectively placed in the subsequent stages of the amplifiers 3611 to 361176, and switches 3631 to 363176 which are connected in parallel between the input ends of the amplifiers 3611 to 361176, and the corresponding output ends of the switches 3621 to 362176 as shown in FIG. 10. The output circuit 360 amplifies the gray scale voltages RV1, GV1 and BV1 to RV176, GV176 and BV176 which are supplied from the D/A converter 350 in time-sharing manner in the order of (RV1 to RV176)→(GV1 to GV176)→(BV1 to BV176) and supplies them to the output terminals S1 to S176 through the switches 3621 to 362176 which are turned ON by the output control signal AS supplied from the controller 200.
Alternatively, the output circuit 360 may supply the gray scale voltages RV1, GV1 and BV1 to RV176, GV176 and BV176 which are supplied from the D/A converter 350 to the output terminals S1 to S176 through the switches 3631 to 363176 which are turned ON by the output control signal AS supplied from the controller 200 through inverters INV1 to INV176. The switches 3621 to 362176 are turned ON when the output control signal AS is “H” level, and the switches 3631 to 363176 are turned OFF when the output control signal AS is “L” level. The output control signal AS is supplied also to the amplifiers 3611 to 361176, so that the amplifiers 3611 to 361176 are in operating state only when the output control signal AS is “H” level. When the output control signal AS is “L” level, the amplifiers 3611 to 361176 are non-operating state to thereby reduce power consumption.
Such an output circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2003-330429, for example.
The operation of the controller 200 and the data driver 300 in the liquid crystal display driving circuit having the above configuration is described hereinafter. First, the operation up to latching of gray scale data by the data latch circuit 330 of the data driver 300 shown in FIG. 9 is described hereinafter without any reference to a timing chart. The control signal generator 220 of the controller 200 shown in FIG. 8 supplies to the data driver 300 a clock HCK, a strobe signal STB, and a horizontal start pulse HST which delays from the strobe signal STB by the length of a pulse of the clock HCK. In the data driver 300 shown in FIG. 9, the shift register 310 thereby performs shift operation for shifting the horizontal start pulse HST in synchronization with the clock HCK and outputs 176 bits of parallel sampling pulses SP1 to SP176. At substantially the same time, the data processor 210 of the controller 200 shown in FIG. 8 converts Red data (Rdata), Green data (Gdata) and Blue data (Bdata) of 6 bit each, which are image data supplied from outside, into gray scale data RD, GD and BD of 6 bit each and supplies them to the data driver 300. As a result, in the data driver 300 shown in FIG. 9, the gray scale data RD, GD and BD are sequentially latched by the data register 320 as gray scale data RD1, GD1 and BD1 to RD176, GD176 and BD176 in synchronization with the sampling pulses SP1 to SP176 supplied from the shift register 310, and then latched by the data latch circuit 330 at a time in synchronization with the rising edge of the strobe signal STB and retained therein for one horizontal period.
The operation in the data driver 300 shown in FIG. 9 from output of the gray scale data from the data latch circuit 330 to supply of the gray scale voltage from the output circuit 360 to each data line is described hereinafter with reference to the timing chart of FIG. 11. At the timing as shown in FIG. 11, the control signal generator 220 of the controller 200 shown in FIG. 8 supplies the switch control signals RS1, GS1 and BS1 and the output control signal AS to the data driver 300, and supplies the switch control signals RS2, GS2 and BS2 to the change-over switches 1071 to 107176 of the liquid crystal panel 100. The switch control signals RS1, GS1 and BS1 respectively have pulse widths which correspond to t10 to t20, t20 to t30 and t30 to t40 which are equally divided (time-shared) portions of time t10 to t40 in one horizontal period. The switch control signals RS2, GS2 and BS2 respectively rise at times t11, t21 and t31 which delay from the rising edges of the switch control signals RS1, GS1 and BS1 by the length of a pulse of the clock HCK and fall at times t13, t23 and t33 which precede the falling edges of the switch control signals RS1, GS1 and BS1 by the length of a pulse of the clock HCK. The output control signal AS rises at times t10, t20 and t30 and falls at times t12, t22 and t32 which are respectively during t11 to t13, t21 to t23 and t31 to t33. The length of “H” level of the output control signal AS at times t10 to t12, t20 to t22 and t30 to t32, which is the operating time of each time-sharing output period of the amplifiers 3611 to 361176 is set to the same predetermined time period determined in consideration of a maximum change in gray scale voltage output before and after the shift of the time-sharing output.
At time t10 when the switch control signal RS1 rises to “H” level, the input terminal a is connected to the output terminal in each of the change-over switches 3411 to 341176 of the switching circuit 340. As a result, the gray scale data RD1 to RD176 which are latched by the data latch circuit 330 are supplied to the D/A converter 350 through the switching circuit 340, then converted into analog gray scale voltages RV1 to RV176 in the D/A converter 350, and supplied to the output circuit 360. The gray scale voltages RV1 to RV176 supplied to the output circuit 360 are amplified by the amplifiers 3611 to 361176 and supplied to the output terminals S1 to S176 through the switches 3621 to 362176 which are turned ON by the output control signal AS which rises to “H” level at the same time as the switch control signal RS1.
At t11 when the switch control signal RS2 rises to “H” level, the input terminal is connected to the output terminal a in the change-over switches 1071 to 107176 of the liquid crystal panel 100. As a result, the gray scale voltages RV1 to RV176 from the output terminals S1 to S176 are supplied to the 176 data lines 101a through the change-over switches 1071 to 107176.
At t12, the voltages of the output terminals S1 to S176 reach target values of the gray scale voltages RV1 to RV176 by the operation of the amplifiers 3611 to 361176 at time t10 to t12. At t12 when the output control signal AS falls to “L” level, the gray scale voltages RV1 to RV176 supplied to the output circuit 360 are supplied to the output terminals S1 to S176 through the ON switches 3631 to 363176. The amplifiers 3611 to 361176 enter the non-operating state to reduce power consumption. Though the amplifiers 3611 to 361176 stay in the non-operating state during t12 to t20, the gray scale voltages RV1 to RV176 are supplied to the output terminals S1 to S176 through the switches 3631 to 363176, and therefore the voltages of the output terminals S1 to S176 remain to be the target values of the gray scale voltages RV1 to RV176.
At t13 when the switch control signal RS2 falls to “L” level, the input terminal is disconnected from the output terminal a in the change-over switches 1071 to 107176 of the liquid crystal panel 100. As a result, the gray scale voltages RV1 to RV176 from the output terminals S1 to S176 are no longer supplied to the 176 data lines 101a. 
At t20 when the switch control signal RS1 falls to “L” level, the input terminal a is disconnected from the output terminal in the change-over switches 3411 to 341176 of the switching circuit 340. Then, at t20 to t30, the gray scale voltages GV1 to GV176 from the output terminals S1 to S176 are supplied to the 176 data lines 101b by the switch control signal GS1, the output control signal AS and the switch control signal GS2 in the same manner as the operation at time t10 to t20 described above.
Further, at t30 to t40, the gray scale voltages BV1 to BV176 from the output terminals S1 to S176 are supplied to the 176 data lines 101c by the switch control signal BS1, the output control signal AS and the switch control signal BS2 in the same manner as the operation at time t10 to t20 described above.
The liquid crystal display driving circuit described above enables control of one pixel of the liquid crystal panel, including three sub-pixels of red (R), green (G) and blue (B), with 1 output by way of outputting gray scale voltages in time sharing manner within one horizontal period.
Regarding such a liquid crystal display driving circuit as described above, there is a demand for further reduction in power consumption. In the above liquid crystal display driving circuit, the operating time for each time-sharing output of the amplifiers 3611 to 361176 shown in FIG. 10 is set to the same predetermined time period which is determined in consideration of a maximum change in gray scale voltage output before and after the shift of the time-sharing output. If a change in gray scale voltage output before and after the shift of the time-sharing output is small, the voltage of the output terminal by the latter output reaches a target value of the gray scale voltage soon. At this time, the amplifiers 3611 to 361176 stay in the operating state until reaching the above predetermined time even after the voltage of the output terminal by the latter output reaches a target value, which causes wasteful power consumption.